Searched refs:nand_info (Results 1 – 5 of 5) sorted by relevance
170 struct mxs_nand_info *nand_info = nand_get_controller_data(chip); in mxs_nand_calc_ecc_layout_by_info() local190 if (geo->ecc_strength > nand_info->max_ecc_strength_supported) in mxs_nand_calc_ecc_layout_by_info()202 struct mxs_nand_info *nand_info = nand_get_controller_data(chip); in mxs_nand_calc_ecc_layout() local235 nand_info->max_ecc_strength_supported); in mxs_nand_calc_ecc_layout()243 static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info) in mxs_nand_wait_for_bch_complete() argument248 ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg, in mxs_nand_wait_for_bch_complete()251 writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr); in mxs_nand_wait_for_bch_complete()269 struct mxs_nand_info *nand_info = nand_get_controller_data(nand); in mxs_nand_cmd_ctrl() local271 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; in mxs_nand_cmd_ctrl()278 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) { in mxs_nand_cmd_ctrl()[all …]
22 static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; variable35 if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[dev] || in get_nand_dev_by_index()36 !nand_info[dev]->name) in get_nand_dev_by_index()39 return nand_info[dev]; in get_nand_dev_by_index()60 nand_info[devnum] = mtd; in nand_register()
71 int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);
96 struct nand_info { struct
30 static struct nand_info spi_nand_tbl[] = {327 static struct nand_info *p_nand_info;331 static struct nand_info *sfc_nand_get_info(u8 *nand_id) in sfc_nand_get_info()