Home
last modified time | relevance | path

Searched refs:ch_cfg (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dspl_boot.c74 setbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_rx_tx()
75 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_rx_tx()
124 clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ in exynos_spi_copy()
127 clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); in exynos_spi_copy()
134 setbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
135 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
138 setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); in exynos_spi_copy()
173 clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); in exynos_spi_copy()
174 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
175 clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); in exynos_spi_copy()
/rk3399_rockchip-uboot/drivers/spi/
H A Dexynos_spi.c48 clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); in spi_flush_fifo()
49 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_flush_fifo()
50 setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); in spi_flush_fifo()
90 setbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_request_bytes()
91 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_request_bytes()
389 reg = readl(&priv->regs->ch_cfg); in exynos_spi_set_mode()
398 writel(reg, &priv->regs->ch_cfg); in exynos_spi_set_mode()
/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Dspi.h15 unsigned int ch_cfg; /* 0x00 */ member
/rk3399_rockchip-uboot/doc/driver-model/
H A Dspi-howto.txt379 reg = readl(&regs->ch_cfg);
388 writel(reg, &regs->ch_cfg);
430 reg = readl(&priv->regs->ch_cfg);
439 writel(reg, &priv->regs->ch_cfg);
481 clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
482 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
483 setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
H A Dspi-howto.rst414 reg = readl(&regs->ch_cfg);
423 writel(reg, &regs->ch_cfg);
469 reg = readl(&priv->regs->ch_cfg);
478 writel(reg, &priv->regs->ch_cfg);
525 clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
526 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
527 setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);