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Searched refs:PCIE3PHY_GRF_PHY0_LN0_CON1 (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c405 #define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004) macro
472 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1); in pcie_cru_init()