Home
last modified time | relevance | path

Searched refs:Fld (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/include/
H A DSA-1100.h280 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
282 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
288 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
320 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
322 #define UDCWC_WC Fld (4, 0) /* Write Count */
324 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
551 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
552 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
592 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
707 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sa1100/
H A Dbitfield.h45 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-pxa/
H A Dbitfield.h45 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
H A Dpxa-regs.h2134 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
2138 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
2143 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2149 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2156 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
2166 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2172 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2192 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
2197 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
[all …]