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Searched refs:FW_DDR_MST1_REG (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3506/
H A Drk3506.c27 #define FW_DDR_MST1_REG 0x24 macro
141 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
142 writel(val & 0xffff00ff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
149 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
150 writel(val & 0xff00ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3528/
H A Drk3528.c18 #define FW_DDR_MST1_REG 0x44 macro
408 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
409 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()