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Searched refs:DSI_PHY_RSTZ (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddw_mipi_dsi.c156 #define DSI_PHY_RSTZ 0xa0 macro
357 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); in mipi_dphy_enableclk_assert()
363 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); in mipi_dphy_enableclk_deassert()
369 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); in mipi_dphy_shutdownz_assert()
375 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); in mipi_dphy_shutdownz_deassert()
381 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); in mipi_dphy_rstz_assert()
387 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); in mipi_dphy_rstz_deassert()
943 dsi_write(dsi, DSI_PHY_RSTZ, 0); in dw_mipi_dsi_post_disable()
H A Drk618_dsi.c109 #define DSI_PHY_RSTZ HOSTREG(0x0054) macro
652 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); in rk618_dsi_pre_enable()
709 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); in rk618_dsi_post_disable()
H A Dinno_video_combo_phy.c199 #define DSI_PHY_RSTZ 0xa0 macro
745 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); in inno_video_phy_ttl_mode_enable()
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_dsi.c1038 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); in mipi_dphy_power_on()
1039 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); in mipi_dphy_power_on()
1040 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); in mipi_dphy_power_on()
1054 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, in mipi_dphy_power_on()
1056 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, in mipi_dphy_power_on()
1058 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); in mipi_dphy_power_on()
H A Drk628_dsi.h129 #define DSI_PHY_RSTZ 0x00a0 macro