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Searched refs:DP_TRAINING_LANE0_SET (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/include/linux/
H A Ddrm_dp_helper.h181 #define DP_TRAINING_LANE0_SET 0x103 macro
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Ddp.c1068 tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val); in tegra_dp_lt_config()
1259 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); in tegra_dc_dp_fast_link_training()
1279 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); in tegra_dc_dp_fast_link_training()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Danalogix_dp.c260 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, in analogix_dp_link_start()
446 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, in analogix_dp_process_clock_recovery()
514 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, in analogix_dp_process_equalizer_training()
H A Ddw-dp.c620 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); in dw_dp_link_train_update_vs_emph()
/rk3399_rockchip-uboot/include/drm/
H A Ddrm_dp_helper.h425 #define DP_TRAINING_LANE0_SET 0x103 macro