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Searched refs:CONFIG_SYS_DDR_TIMING_5_1333 (Results 1 – 3 of 3) sorted by relevance

/rk3399_rockchip-uboot/include/configs/
H A DBSC9132QDS.h159 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 macro
195 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A Dspl_minimal.c60 __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); in sdram_init()
/rk3399_rockchip-uboot/scripts/
H A Dconfig_whitelist.txt2770 CONFIG_SYS_DDR_TIMING_5_1333