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Searched refs:set_val (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/mminfra/mt8196/
H A Dmminfra.c43 .set_val = SPM_SEMA_MMINFRA,
49 static int spm_semaphore_get(uint32_t base, uint32_t set_val) in spm_semaphore_get() argument
55 if ((val & set_val) == set_val) { in spm_semaphore_get()
57 base, val, set_val); in spm_semaphore_get()
62 mmio_write_32(base, set_val); in spm_semaphore_get()
64 if ((mmio_read_32(base) & set_val) == set_val) in spm_semaphore_get()
69 mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val); in spm_semaphore_get()
73 static int spm_semaphore_release(uint32_t base, uint32_t set_val) in spm_semaphore_release() argument
79 if ((val & set_val) != set_val) { in spm_semaphore_release()
81 base, val, set_val); in spm_semaphore_release()
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H A Dmminfra.h42 uint32_t set_val; member
/rk3399_ARM-atf/plat/ti/k3low/common/drivers/k3-ddrss/
H A Dam62l_ddrss.c115 uint32_t set_val; in set_ddr_pll_div() local
119 set_val = (reg_val & ~PLL_HSDIV_RESET_MASK) | FIELD_PREP(PLL_HSDIV_RESET_MASK, 1); in set_ddr_pll_div()
120 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()
124 set_val = (reg_val & ~PLL_HSDIV_DIV_MASK) | FIELD_PREP(PLL_HSDIV_DIV_MASK, div); in set_ddr_pll_div()
125 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()
129 set_val = (reg_val & ~PLL_HSDIV_CLKOUT_MASK) | FIELD_PREP(PLL_HSDIV_CLKOUT_MASK, 1); in set_ddr_pll_div()
130 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()
134 set_val = (reg_val & ~PLL_HSDIV_RESET_MASK) | FIELD_PREP(PLL_HSDIV_RESET_MASK, 0); in set_ddr_pll_div()
135 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_rv_pwr_ctrl.c20 uint32_t retry_times, uint32_t set_reg, uint32_t set_val) in wait_for_state_ready() argument
41 mmio_write_32(set_reg, set_val); in wait_for_state_ready()