Searched refs:div2 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/ |
| H A D | apupwr_clkctl.h | 16 int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);
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| H A D | apupwr_clkctl.c | 200 int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain) in apupwr_smc_pll_set_rate() argument
251 anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()
253 if (div2) { in apupwr_smc_pll_set_rate()
307 __func__, __LINE__, domain, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()
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| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | asm_macros.S | 227 div2: label
233 bhs div2
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | pm_api_clock.c | 2748 const enum clock_id div2; member
2759 .div2 = CLK_IOPLL_INT_MUX,
2766 .div2 = CLK_RPLL_INT_MUX,
2773 .div2 = CLK_APLL_INT_MUX,
2780 .div2 = CLK_VPLL_INT_MUX,
2787 .div2 = CLK_DPLL_INT_MUX,
2852 (pm_plls[i].div2 == clock_id) || in pm_clock_get_pll_by_related_clk()
2989 if (pll->div2 == clock_id) { in pm_clock_pll_set_parent()
3031 if (pll->div2 == clock_id) { in pm_clock_pll_get_parent()
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