| /rk3399_ARM-atf/drivers/ti/ti_sci/ |
| H A D | ti_sci.h | 150 int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id,
153 int ti_sci_clock_idle(uint32_t dev_id, uint8_t clk_id);
154 int ti_sci_clock_put(uint32_t dev_id, uint8_t clk_id);
155 int ti_sci_clock_is_auto(uint32_t dev_id, uint8_t clk_id,
157 int ti_sci_clock_is_on(uint32_t dev_id, uint8_t clk_id,
159 int ti_sci_clock_is_off(uint32_t dev_id, uint8_t clk_id,
161 int ti_sci_clock_set_parent(uint32_t dev_id, uint8_t clk_id,
163 int ti_sci_clock_get_parent(uint32_t dev_id, uint8_t clk_id,
165 int ti_sci_clock_get_num_parents(uint32_t dev_id, uint8_t clk_id,
167 int ti_sci_clock_get_match_freq(uint32_t dev_id, uint8_t clk_id,
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| H A D | ti_sci.c | 691 int ti_sci_clock_set_state(uint32_t dev_id, uint8_t clk_id, in ti_sci_clock_set_state() argument
709 req.dev_id = dev_id; in ti_sci_clock_set_state()
734 int ti_sci_clock_get_state(uint32_t dev_id, uint8_t clk_id, in ti_sci_clock_get_state() argument
756 req.dev_id = dev_id; in ti_sci_clock_get_state()
786 int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id, in ti_sci_clock_get() argument
796 return ti_sci_clock_set_state(dev_id, clk_id, flags, in ti_sci_clock_get()
812 int ti_sci_clock_idle(uint32_t dev_id, uint8_t clk_id) in ti_sci_clock_idle() argument
814 return ti_sci_clock_set_state(dev_id, clk_id, 0, in ti_sci_clock_idle()
830 int ti_sci_clock_put(uint32_t dev_id, uint8_t clk_id) in ti_sci_clock_put() argument
832 return ti_sci_clock_set_state(dev_id, clk_id, 0, in ti_sci_clock_put()
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| H A D | ti_sci_protocol.h | 299 uint32_t dev_id; member
320 uint32_t dev_id; member
358 uint32_t dev_id; member
375 uint32_t dev_id; member
406 uint32_t dev_id; member
446 uint32_t dev_id; member
502 uint32_t dev_id; member
523 uint32_t dev_id; member
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| /rk3399_ARM-atf/plat/mediatek/drivers/iommu/ |
| H A D | mtk_iommu_smc.c | 97 uint32_t dev_id, reg_addr, reg_mask; in mtk_infra_master_config_sec() local
105 for (dev_id = 0U; dev_id < g_ifr_mst_num; dev_id++) { in mtk_infra_master_config_sec()
106 if ((dev_id_msk & BIT(dev_id)) == 0U) { in mtk_infra_master_config_sec()
110 ifr_cfg = &g_ifr_mst_cfg[dev_id]; in mtk_infra_master_config_sec()
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| /rk3399_ARM-atf/include/drivers/nxp/dcfg/ |
| H A D | dcfg.h | 43 uint32_t dev_id:6; member
47 uint32_t dev_id:12; member
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| /rk3399_ARM-atf/plat/st/stm32mp1/ |
| H A D | stm32mp1_private.c | 303 uint32_t dev_id; in stm32mp_get_chip_dev_id() local
305 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { in stm32mp_get_chip_dev_id()
307 dev_id = STM32MP1_CHIP_ID; in stm32mp_get_chip_dev_id()
310 return dev_id; in stm32mp_get_chip_dev_id()
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/ |
| H A D | mt_cpu_pm_cpc.c | 302 uint64_t mtk_cpc_prof_dev_name(unsigned int dev_id) in mtk_cpc_prof_dev_name() argument
319 while ((prof_dev_name[dev_id][i] != '\0') && (i < PROF_DEV_NAME_LEN)) { in mtk_cpc_prof_dev_name()
320 tran = (uint64_t)(prof_dev_name[dev_id][i] & 0xFF); in mtk_cpc_prof_dev_name()
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| /rk3399_ARM-atf/drivers/cadence/nand/ |
| H A D | cdns_nand.c | 224 dev_info.dev_id = FIELD_GET(CNF_DEV_ID_MASK, reg); in cdns_nand_update_dev_info()
226 INFO(" -- Device ID: 0x%02x\n", dev_info.dev_id); in cdns_nand_update_dev_info()
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| /rk3399_ARM-atf/include/drivers/cadence/ |
| H A D | cdns_nand.h | 28 uint8_t dev_id; member
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