1050a99a6SPankaj Gupta /* 2df02aeeeSBiwen Li * Copyright 2018-2022 NXP 3050a99a6SPankaj Gupta * 4050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5050a99a6SPankaj Gupta * 6050a99a6SPankaj Gupta */ 7050a99a6SPankaj Gupta 8050a99a6SPankaj Gupta #ifndef DCFG_H 9050a99a6SPankaj Gupta #define DCFG_H 10050a99a6SPankaj Gupta 11050a99a6SPankaj Gupta #include <endian.h> 12050a99a6SPankaj Gupta 13050a99a6SPankaj Gupta #if defined(CONFIG_CHASSIS_2) 14050a99a6SPankaj Gupta #include <dcfg_lsch2.h> 15df02aeeeSBiwen Li #elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) 16050a99a6SPankaj Gupta #include <dcfg_lsch3.h> 17050a99a6SPankaj Gupta #endif 18050a99a6SPankaj Gupta 19050a99a6SPankaj Gupta #ifdef NXP_GUR_BE 20050a99a6SPankaj Gupta #define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 21050a99a6SPankaj Gupta #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 22050a99a6SPankaj Gupta #elif defined(NXP_GUR_LE) 23050a99a6SPankaj Gupta #define gur_in32(a) mmio_read_32((uintptr_t)(a)) 24050a99a6SPankaj Gupta #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v) 25050a99a6SPankaj Gupta #else 26050a99a6SPankaj Gupta #error Please define CCSR GUR register endianness 27050a99a6SPankaj Gupta #endif 28050a99a6SPankaj Gupta 29050a99a6SPankaj Gupta typedef struct { 3008695df9SJiafei Pan union { 3108695df9SJiafei Pan uint32_t val; 3208695df9SJiafei Pan struct { 3308695df9SJiafei Pan uint32_t min_ver:4; 3408695df9SJiafei Pan uint32_t maj_ver:4; 3508695df9SJiafei Pan #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 3608695df9SJiafei Pan uint32_t personality:6; 3708695df9SJiafei Pan uint32_t rsv1:2; 3808695df9SJiafei Pan #elif defined(CONFIG_CHASSIS_2) 3908695df9SJiafei Pan uint32_t personality:8; 4008695df9SJiafei Pan 41050a99a6SPankaj Gupta #endif 4208695df9SJiafei Pan #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 4308695df9SJiafei Pan uint32_t dev_id:6; 4408695df9SJiafei Pan uint32_t rsv2:2; 4508695df9SJiafei Pan uint32_t family:4; 4608695df9SJiafei Pan #elif defined(CONFIG_CHASSIS_2) 4708695df9SJiafei Pan uint32_t dev_id:12; 4808695df9SJiafei Pan #endif 4908695df9SJiafei Pan uint32_t mfr_id; 5008695df9SJiafei Pan } __packed bf; 5108695df9SJiafei Pan struct { 5208695df9SJiafei Pan uint32_t maj_min:8; 5308695df9SJiafei Pan uint32_t version; /* SoC version without major and minor info */ 5408695df9SJiafei Pan } __packed bf_ver; 5508695df9SJiafei Pan } __packed svr_reg; 56050a99a6SPankaj Gupta bool sec_enabled; 5708695df9SJiafei Pan bool is_populated; 58050a99a6SPankaj Gupta } soc_info_t; 59050a99a6SPankaj Gupta 60050a99a6SPankaj Gupta typedef struct { 61050a99a6SPankaj Gupta bool is_populated; 62050a99a6SPankaj Gupta uint8_t ocram_present; 63050a99a6SPankaj Gupta uint8_t ddrc1_present; 6408695df9SJiafei Pan #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 65050a99a6SPankaj Gupta uint8_t ddrc2_present; 66050a99a6SPankaj Gupta #endif 67050a99a6SPankaj Gupta } devdisr5_info_t; 68050a99a6SPankaj Gupta 69050a99a6SPankaj Gupta typedef struct { 70050a99a6SPankaj Gupta uint32_t porsr1; 71050a99a6SPankaj Gupta uintptr_t g_nxp_dcfg_addr; 72050a99a6SPankaj Gupta unsigned long nxp_sysclk_freq; 73050a99a6SPankaj Gupta unsigned long nxp_ddrclk_freq; 74050a99a6SPankaj Gupta unsigned int nxp_plat_clk_divider; 75050a99a6SPankaj Gupta } dcfg_init_info_t; 76050a99a6SPankaj Gupta 77050a99a6SPankaj Gupta 78050a99a6SPankaj Gupta struct sysinfo { 79050a99a6SPankaj Gupta unsigned long freq_platform; 80050a99a6SPankaj Gupta unsigned long freq_ddr_pll0; 81050a99a6SPankaj Gupta unsigned long freq_ddr_pll1; 82050a99a6SPankaj Gupta }; 83050a99a6SPankaj Gupta 84050a99a6SPankaj Gupta int get_clocks(struct sysinfo *sys); 85050a99a6SPankaj Gupta 86050a99a6SPankaj Gupta /* Read the PORSR1 register */ 87050a99a6SPankaj Gupta uint32_t read_reg_porsr1(void); 88050a99a6SPankaj Gupta 89050a99a6SPankaj Gupta /******************************************************************************* 90050a99a6SPankaj Gupta * Returns true if secur eboot is enabled on board 91050a99a6SPankaj Gupta * mode = 0 (development mode - sb_en = 1) 92050a99a6SPankaj Gupta * mode = 1 (production mode - ITS = 1) 93050a99a6SPankaj Gupta ******************************************************************************/ 94050a99a6SPankaj Gupta bool check_boot_mode_secure(uint32_t *mode); 95050a99a6SPankaj Gupta 96*2535e204SElyes Haouas const soc_info_t *get_soc_info(void); 97*2535e204SElyes Haouas const devdisr5_info_t *get_devdisr5_info(void); 98050a99a6SPankaj Gupta 99050a99a6SPankaj Gupta void dcfg_init(dcfg_init_info_t *dcfg_init_data); 100050a99a6SPankaj Gupta bool is_sec_enabled(void); 101050a99a6SPankaj Gupta 102050a99a6SPankaj Gupta void error_handler(int error_code); 103050a99a6SPankaj Gupta #endif /* DCFG_H */ 104