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Searched refs:ari_base (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dari.c44 static inline uint32_t ari_read_32(uint32_t ari_base, uint32_t reg) in ari_read_32() argument
46 return mmio_read_32((uint64_t)ari_base + (uint64_t)reg); in ari_read_32()
49 static inline void ari_write_32(uint32_t ari_base, uint32_t val, uint32_t reg) in ari_write_32() argument
51 mmio_write_32((uint64_t)ari_base + (uint64_t)reg, val); in ari_write_32()
54 static inline uint32_t ari_get_request_low(uint32_t ari_base) in ari_get_request_low() argument
56 return ari_read_32(ari_base, ARI_REQUEST_DATA_LO); in ari_get_request_low()
59 static inline uint32_t ari_get_request_high(uint32_t ari_base) in ari_get_request_high() argument
61 return ari_read_32(ari_base, ARI_REQUEST_DATA_HI); in ari_get_request_high()
64 static inline uint32_t ari_get_response_low(uint32_t ari_base) in ari_get_response_low() argument
66 return ari_read_32(ari_base, ARI_RESPONSE_DATA_LO); in ari_get_response_low()
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H A Dnvg.c19 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_enter_cstate() argument
24 (void)ari_base; in nvg_enter_cstate()
47 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, in nvg_update_cstate_info() argument
53 (void)ari_base; in nvg_update_cstate_info()
89 int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) in nvg_update_crossover_time() argument
93 (void)ari_base; in nvg_update_crossover_time()
113 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) in nvg_read_cstate_stats() argument
117 (void)ari_base; in nvg_read_cstate_stats()
137 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) in nvg_write_cstate_stats() argument
141 (void)ari_base; in nvg_write_cstate_stats()
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H A Dmce.c76 uint32_t ari_base; member
84 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_0_OFFSET,
89 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_1_OFFSET,
94 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_2_OFFSET,
99 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_3_OFFSET,
104 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_4_OFFSET,
109 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_5_OFFSET,
131 return mce_cfg_table[cpuid].ari_base; in mce_get_curr_cpu_ari_base()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/include/
H A Dmce_private.h89 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state,
95 int32_t (*update_cstate_info)(uint32_t ari_base,
107 int32_t (*update_crossover_time)(uint32_t ari_base,
114 uint64_t (*read_cstate_stats)(uint32_t ari_base,
120 int32_t (*write_cstate_stats)(uint32_t ari_base,
127 uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd,
136 int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
146 int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
153 int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid);
158 int32_t (*cc3_ctrl)(uint32_t ari_base,
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