Searched refs:S32CC_CLK_MC_CGM0_MUX0 (Results 1 – 3 of 3) sorted by relevance
82 #define S32CC_CLK_MC_CGM0_MUX0 S32CC_ARCH_CLK(6) macro
110 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1); in enable_xbar_clk()
232 [S32CC_CLK_ID(S32CC_CLK_MC_CGM0_MUX0)] = &cgm0_mux0_clk,