Searched refs:S32CC_CLK_DDR_PLL_PHI0 (Results 1 – 3 of 3) sorted by relevance
164 ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL); in setup_ddr_pll()176 ret = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_DDR_PLL_PHI0); in enable_ddr_clk()
180 S32CC_CLK_DDR_PLL_PHI0,215 [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_PHI0)] = &ddr_pll_phi0_clk,
62 #define S32CC_CLK_DDR_PLL_PHI0 S32CC_HW_CLK(36) macro