Searched refs:S32CC_CLK_DDR_PLL_MUX (Results 1 – 3 of 3) sorted by relevance
99 #define S32CC_CLK_DDR_PLL_MUX S32CC_ARCH_CLK(18) macro
154 ret = clk_set_parent(S32CC_CLK_DDR_PLL_MUX, S32CC_CLK_FXOSC); in setup_ddr_pll()
252 [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_MUX)] = &ddr_pll_mux_clk,