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Searched refs:RCC_PLLNCFGR1_DIVM_SHIFT (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp1_clk.c1055 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; in stm32mp1_pll_get_fvco()
1766 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & in stm32mp1_check_pll_conf()
1897 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & in stm32mp1_pll_config()
H A Dclk-stm32mp13.c1218 *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK; in clk_stm32_pll_compute_cfgr1()
1712 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; in clk_stm32_pll_recalc_rate()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp13_rcc.h1762 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 macro
H A Dstm32mp15_rcc.h2289 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 macro