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Searched refs:RCC_MPCKDIVR (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp1_clk.c132 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 31),
1124 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); in get_clock_rate()
H A Dclk-stm32mp13.c797 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 0, NULL, DIV_NO_BIT_RDY),
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp13_rcc.h64 #define RCC_MPCKDIVR U(0X564) macro
H A Dstm32mp15_rcc.h20 #define RCC_MPCKDIVR U(0x2C) macro