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Searched refs:MVEBU_NB_GPIO1_SEL_REG (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dplat_pm.c31 #define MVEBU_NB_GPIO1_SEL_REG (MVEBU_NB_REGS_BASE + 0x830) macro
548 mmio_clrbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_UART1_SEL); in a3700_pm_src_uart1()
550 mmio_setbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_GPIO_19_EN); in a3700_pm_src_uart1()
554 mmio_setbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_GPIO_18_EN); in a3700_pm_src_uart1()
564 mmio_setbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_GPIO_25_26_EN); in a3700_pm_src_uart0()