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/rk3399_ARM-atf/docs/components/
H A Dgranule-protection-tables-design.rst93 GPT L1 entries having the same PAS. The maximum size of
120 ``GPT_MAP_REGION_GRANULE`` creates a region using L0 and L1 mappings.
153 During Granule Transition access to L1 tables is controlled by a lock to ensure
157 structure. Setting this option to 0 chooses a single spinlock for all GPT L1
175 are then added to the L1 PAS regions to be initialized in the next step and
187 all GPT L1 table entries(``RME_GPT_BITLOCK_BLOCK`` is 0) and are passed as zero
231 The L1 memory also has some constraints.
233 * The L1 tables must be aligned to their size. The size of each L1 table is the
236 * There must be enough L1 memory supplied to build all requested L1 tables.
237 * The L1 memory must fall within a PAS of type GPT_GPI_ROOT.
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/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-juno.rst323 last CPUs in their respective clusters to power down, therefore both the L1 and
363 the cache associated with power level 0 is flushed (L1).
387 flush of both L1 and L2 caches.
395 level 0, which only requires L1 cache flush.
417 only necessary to flush the cache to power level 0 (L1). This is the best case
456 powers down to the cluster level, requiring a flush of both L1 and L2 caches.
460 an L1 cache flush.
/rk3399_ARM-atf/docs/plat/
H A Drz-g2.rst47 ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB
48 ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K
H A Dnvidia-tegra.rst35 micro-ops can be executed per clock), and includes a 128KB 4-way L1
36 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
H A Drcar-gen3.rst43 ARM CA57 (ARMv8) 1.5 GHz quad core, with NEON/VFPv4, L1$ I/D
45 ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K,
/rk3399_ARM-atf/docs/plat/nxp/
H A Dnxp-layerscape.rst103 Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high
/rk3399_ARM-atf/docs/design/
H A Dcpu-specific-build-macros.rst1227 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
1228 of the L2 by set/way flushes any dirty lines from the L1 as well. This
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_csr_all_cdefines.h6805 #define L1 0x100U macro
/rk3399_ARM-atf/docs/getting_started/
H A Dbuild-options.rst977 - and it chooses a single spinlock for all GPT L1 table entries. Default
/rk3399_ARM-atf/docs/
H A Dchange-log.md2674 …- flush L1/L2/L3/Sys cache before HPS cold reset ([7ac7dad](https://review.trustedfirmware.org/plu…