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Searched refs:GICR_CTLR_RWP_BIT (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dcm3_system_reset.c93 if ((a3700_gicr_read(proc, GICR_CTLR) & GICR_CTLR_RWP_BIT) != 0U) { in a3700_gic_redist_disable_irqs()
/rk3399_ARM-atf/include/drivers/arm/
H A Dgicv3.h209 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT) macro
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgicv3_private.h347 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { in gicr_wait_for_pending_write()