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/rk3399_ARM-atf/docs/design/
H A Dinterrupt-framework-design.rst11 the interrupt to either software in EL3 or Secure-EL1 depending upon the
21 knowledge of software executing in Secure-EL1/Secure-EL0. The choice of
35 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
36 Secure-EL1 depending upon the security state of the current execution
37 context. It is always handled in Secure-EL1.
40 Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the
41 current execution context. It is always handled in either Non-secure EL1
44 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
85 for GIC version 3.0 (Arm GICv3) and only the Secure-EL1 and Non-secure interrupt
95 Secure-EL1 interrupts
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H A Dfirmware-design.rst55 - Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
227 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
314 #. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
320 BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
329 for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
386 AArch64 BL32 (Secure-EL1 Payload) image load
395 Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
431 as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
550 AArch64 BL32 (Secure-EL1 Payload) image initialization
553 If a BL32 image is present then there must be a matching Secure-EL1 Payload
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/rk3399_ARM-atf/docs/components/
H A Dsecure-partition-manager.rst39 the secure world, managing multiple S-EL1 or S-EL0 partitions `[5]`_.
40 #. EL3 SPMC based on the FF-A specification, managing a single S-EL1 partition
54 S-EL1 or S-EL2:
58 - The same SPMD component is used for both S-EL1 and S-EL2 SPMC configurations.
63 - S-EL1 SPMC for platforms not supporting the FEAT_SEL2 architecture
64 extension. The SPMD relays the FF-A protocol from EL3 to S-EL1.
73 SPMC located at S-EL1, S-EL2 or EL3:
83 SPMC exception level is set to S-EL1.
97 | SPMC at S-EL1 | 0 | 0 | 0 |
123 Sample TF-A build command line when the SPMC is located at S-EL1
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H A Dsecure-partition-manager-mm.rst36 privileged Exception Level (i.e. EL3 or S-EL1) makes security auditing of
120 Payload image executing at S-EL1 (e.g. a Trusted OS). Both are referred to as
258 A SVC causes an exception to be taken to S-EL1. TF-A assumes ownership of S-EL1
259 and installs a simple exception vector table in S-EL1 that relays a SVC request
294 the Secure EL1&0 translation regime).
403 description and initialises the Secure EL1&0 translation regime as follows.
422 S-EL0 or S-EL1.
484 buffer will be mapped in the Secure EL1&0 translation regime with read-only
556 The buffer is mapped in the Secure EL1&0 translation regime with read-only
602 the Secure EL1&0 Translation regime with appropriate memory attributes.
[all …]
H A Del3-spmc.rst14 - Manages a single S-EL1 Secure Partition
16 - Provides support for EL3 Logical Partitions to support easy migration from EL3 to S-EL1.
23 and SPMC at EL3, one S-EL1 secure partition, with an optional
46 - BL32 option is re-purposed to specify the S-EL1 TEE or SP image.
159 exception-level = <0x2>; /* S-EL1 */
456 SPMC only supports a single Pinned MP S-EL1 SP. The *execution-ctx-count*
465 - SPMC is capable of forwarding Secure interrupt to S-EL1 SP
468 - Interrupt Number is not passed, S-EL1 SP can access the GIC registers directly.
H A Dcontext-management-library.rst39 (EL2/EL1, vector, general-purpose registers), will be overwritten, as the software
80 EL3 should initialise and monitor S-EL2 registers only. S-EL1 registers should
82 absent, S-EL1 registers should be initialised from EL3.
426 EL1 Registers
433 at EL3 to facilitate the saving and restoration of the EL1 system registers
490 in any EL2 registers that are necessary for execution in EL1 with no EL2 present.
542 EL3 from NS world, the EL1 and EL2 system registers which might be modified in
543 lower exception levels NS(EL2/EL1) will carry forward those values to EL3.
545 world, written during the previous ERET from EL3 to NS(EL2/EL1).
H A Dplatform-interrupt-controller-API.rst153 Secure EL1 interrupts.
156 for Secure EL1 interrupts.
173 - ``INTR_TYPE_S_EL1``: interrupt is meant to be consumed by Secure EL1.
H A Dexception-handling.rst147 - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of
149 EL3. As a result, S-EL1 software cannot expect to handle Non-secure
150 interrupts at S-EL1. Essentially, this deprecates the routing mode described
153 In order for S-EL1 software to handle Non-secure interrupts while having
156 handled over to S-EL1.
489 to be taken to S-EL1 [#irq]_, so would get a chance to populate the designated
500 .. [#irq] In case of GICv2, Non-secure interrupts while in S-EL1 were signalled
H A Dxlat-tables-lib-v2-design.rst74 the EL1&0 translation regime, the attributes also specify whether the region is
75 a User region (EL0) or Privileged region (EL1). See the ``MT_xxx`` definitions
76 in ``xlat_tables_v2.h``. Note that for the EL1&0 translation regime the Execute
77 Never attribute is set simultaneously for both EL1 and EL0.
111 create translation tables pertaining to the S-EL1&0 translation regime.
H A Darm-sip-service.rst37 Exception Level (either EL2, or NS EL1 if EL2 isn't implemented) to request to
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-3.rst5 | Title | RO memory is always executable at AArch64 Secure EL1 |
15 | Affected | executing at AArch64 Secure EL1 |
34 This feature does not work correctly for AArch64 images executing at Secure EL1.
58 determine whether a region is executable. The Secure EL1&0 translation regime
61 in the Secure EL1&0 regime. As a result, this programs the Secure EL0 execution
62 permissions but always leaves the memory as executable at Secure EL1.
H A Dsecurity-advisory-tfv-2.rst43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
44 interface. Therefore this issue only exists for AArch32 Secure EL1 code when
50 from AArch32 Secure EL1.
H A Dsecurity-advisory-tfv-6.rst54 Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is
76 disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.
81 at invalidating the branch predictor on Cortex-A57, the drop into Secure-EL1
98 | ``PSCI_VERSION`` with "BPIALL at AArch32 Secure-EL1" | 1276 |
100 | ``SMCCC_ARCH_WORKAROUND_1`` with "BPIALL at AArch32 Secure-EL1" | 770 |
131 translation regime, for example between EL0 and EL1, therefore this variant
H A Dsecurity-advisory-tfv-5.rst39 transitioning to S-EL1.
50 NOTE: The original pull request referenced above only fixed the issue for S-EL1
/rk3399_ARM-atf/plat/arm/board/fvp/fdts/
H A Dfvp_cactus_sp_manifest.dts23 exception-level = <2>; /* S-EL1 */
H A Doptee_sp_manifest.dts22 exception-level = <2>; /* S-EL1 */
/rk3399_ARM-atf/services/std_svc/spm/el3_spmc/
H A Dspmc.h83 EL1 = 0, enumerator
/rk3399_ARM-atf/docs/perf/
H A Dperformance-monitoring-unit.rst79 - If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
85 Non-secure EL1.
/rk3399_ARM-atf/docs/getting_started/
H A Drt-svc-writers-guide.rst285 The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow
305 Secure-EL1 Payload Dispatcher service (SPD)
309 or other Secure-EL1 Payload are special. These services need to manage the
310 Secure-EL1 context, provide the *Secure Monitor* functionality of switching
311 between the normal and secure worlds, deliver SMC Calls through to Secure-EL1
312 and generally manage the Secure-EL1 Payload through CPU power-state transitions.
H A Dimage-terminology.rst74 Secure-EL1 Payload (SP): ``AP_BL32``
78 normal world. However, it may refer to a more abstract Secure-EL1 Payload (SP).
80 single or primary image executing at Secure-EL1. In systems where there are
/rk3399_ARM-atf/docs/components/spd/
H A Doptee-dispatcher.rst4 `OP-TEE OS`_ is a Trusted OS running as Secure EL1.
H A Dtlk-dispatcher.rst20 TLK is a Trusted OS running as Secure EL1. It is a Free Open Source Software
/rk3399_ARM-atf/docs/plat/
H A Dimx8m.rst99 causes those locations not to be filled, which in turn causing EL1&0 software
103 data exchange between EL3 and EL1&0 software.
/rk3399_ARM-atf/docs/process/
H A Dsecurity.rst52 | |TFV-3| | RO memory is always executable at AArch64 Secure EL1 |
/rk3399_ARM-atf/docs/plat/nxp/
H A Dnxp-layerscape.rst179 + EL1 BL32(Tee OS) | kernel
195 + EL1 fip-ddr BL32(Tee OS) | kernel
219 | Secure EL1 Payload Shared Memory (2 MB) |

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