Searched refs:DDR_PHYA_MASTER0_CALBUSY (Results 1 – 2 of 2) sorted by relevance
105 #define DDR_PHYA_MASTER0_CALBUSY 0x4038165CU macro
145 err = mmio_read_32_poll_timeout(DDR_PHYA_MASTER0_CALBUSY, calbusy_reg, in post_train_setup()