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Searched refs:CPU_PM_ASSERT (Results 1 – 8 of 8) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_ppu.c22 CPU_PM_ASSERT(ctrl); in mt_smp_ppu_pwr_dynamic_set()
30 CPU_PM_ASSERT(ctrl); in mt_smp_ppu_pwr_static_set()
39 CPU_PM_ASSERT(ctrl); in mt_smp_ppu_pwr_set()
55 CPU_PM_ASSERT(ctrl); in mt_smp_ppu_op_set()
76 CPU_PM_ASSERT(ctrl); in mt_smp_ppu_set()
H A Dmt_smp.c29 CPU_PM_ASSERT(cluster == 0); in mt_smp_core_init_arch()
30 CPU_PM_ASSERT(pwr_ctrl); in mt_smp_core_init_arch()
47 CPU_PM_ASSERT(pwr_ctrl); in mt_smp_core_bootup_address_set()
58 CPU_PM_ASSERT(pwr_ctrl); in mt_smp_power_core_on()
H A Dmt_cpu_pm.c177 CPU_PM_ASSERT(cpu < PLATFORM_CORE_COUNT); in cpupm_cpu_ildo_state_valid()
224 CPU_PM_ASSERT(state); in cpupm_cpu_resume_common()
267 CPU_PM_ASSERT(state); in cpupm_cpu_resume_smp()
283 CPU_PM_ASSERT(state); in cpupm_cpu_suspend_smp()
522 CPU_PM_ASSERT(0); in mcusys_prepare_resume()
545 CPU_PM_ASSERT(state); in cpupm_do_pstate_off()
546 CPU_PM_ASSERT(state->pwr.afflv <= PLAT_MAX_PWR_LVL); in cpupm_do_pstate_off()
583 CPU_PM_ASSERT(state); in cpupm_do_pstate_on()
586 CPU_PM_ASSERT(0); in cpupm_do_pstate_on()
591 CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SYSTEM_MCUSYS] >= 0); in cpupm_do_pstate_on()
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H A Dmt_cpu_pm.h40 #define CPU_PM_ASSERT(_cond) ({ \ macro
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_smp.c27 CPU_PM_ASSERT(cluster == 0); in mt_smp_core_init_arch()
28 CPU_PM_ASSERT(pwr_ctrl != NULL); in mt_smp_core_init_arch()
40 CPU_PM_ASSERT(pwr_ctrl != NULL); in mt_smp_core_bootup_address_set()
51 CPU_PM_ASSERT(pwr_ctrl); in mt_smp_power_core_on()
H A Dmt_cpu_pm.c64 CPU_PM_ASSERT(state != NULL); in cpupm_cpu_resume_common()
83 CPU_PM_ASSERT(state != NULL); in cpupm_cpu_resume_smp()
96 CPU_PM_ASSERT(state != NULL); in cpupm_cpu_suspend_smp()
207 CPU_PM_ASSERT(0); in cpupm_do_pstate_off()
261 CPU_PM_ASSERT(state != NULL); in cpupm_do_pstate_on()
264 CPU_PM_ASSERT(0); in cpupm_do_pstate_on()
282 CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SYSTEM_MEM] >= 0); in cpupm_do_pstate_on()
286 CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SYSTEM_PLL] >= 0); in cpupm_do_pstate_on()
290 CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SYSTEM_BUS] >= 0); in cpupm_do_pstate_on()
294 CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SUSPEND] >= 0); in cpupm_do_pstate_on()
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H A Dmt_smp.h22 CPU_PM_ASSERT(k_cnt < SMP_CORE_TIMEOUT_MAX); \
H A Dmt_cpu_pm.h32 #define CPU_PM_ASSERT(_cond) ({ \ macro