Searched refs:CLKMGR_PLLCX_DIV_MSK (Results 1 – 2 of 2) sorted by relevance
417 clock /= (mmio_read_32(mainpllc_reg) & CLKMGR_PLLCX_DIV_MSK); in get_clk_freq()422 clock /= (mmio_read_32(perpllc_reg) & CLKMGR_PLLCX_DIV_MSK); in get_clk_freq()579 clock /= 1 + (mmio_read_32(ctr_reg) & CLKMGR_PLLCX_DIV_MSK); in get_mpu_clk()
224 #define CLKMGR_PLLCX_DIV_MSK GENMASK(10, 0) macro