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Searched refs:B_GIPC3_SETCLR_1 (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/vcp/rv/
H A Dmmup_common.c22 (mmio_read_32(VCP_R_GIPC_IN_SET) & B_GIPC3_SETCLR_1) == 0 && in mmup_smc_rstn_set()
23 (mmio_read_32(VCP_R_GIPC_IN_CLR) & B_GIPC3_SETCLR_1) == 0 && in mmup_smc_rstn_set()
H A Dvcp_common.c111 (mmio_read_32(VCP_R_GIPC_IN_SET) & B_GIPC3_SETCLR_1) == 0 && in vcp_smc_rstn_set()
112 (mmio_read_32(VCP_R_GIPC_IN_CLR) & B_GIPC3_SETCLR_1) == 0 && in vcp_smc_rstn_set()
/rk3399_ARM-atf/plat/mediatek/drivers/vcp/mt8196/
H A Dvcp_reg.h34 #define B_GIPC3_SETCLR_1 BIT(13) macro