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Searched refs:BCLK_CG_EN_LSB (Results 1 – 12 of 12) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_pmic_wrap.c117 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase()
140 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
H A Dmt_spm_reg.h607 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_pmic_wrap.c119 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase()
137 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
H A Dmt_spm_reg.h21 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_pmic_wrap.c123 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase()
149 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
H A Dmt_spm_reg.h496 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_pmic_wrap.c117 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase()
140 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
H A Dmt_spm_reg.h630 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ macro
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm_pmic_wrap.c131 BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase()
153 BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
H A Dspm.h418 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_reg.h762 #define BCLK_CG_EN_LSB BIT(0) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_reg.h546 #define BCLK_CG_EN_LSB BIT(0) /* 1b */ macro