| /optee_os/core/arch/arm/crypto/ |
| H A D | aes_modes_armv8a_ce_a64.S | 152 encrypt_block2x v0, v1, w3, x2, x6, w7
157 decrypt_block2x v0, v1, w3, x2, x6, w7
164 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
169 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
198 encrypt_block2x v0, v1, w3, x2, x6, w7
202 decrypt_block2x v0, v1, w3, x2, x6, w7
206 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
210 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
329 encrypt_block v0, w3, x2, x6, w7
331 encrypt_block v1, w3, x2, x6, w7
[all …]
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| H A D | sm4_armv8a_aese_a64.S | 484 mov w7, v5.s[1]
486 eor w8, w8, w7
487 mov w7, v5.s[2]
488 eor w8, w8, w7
489 mov w7, v5.s[3]
490 eor w8, w8, w7
495 mov w7, TMP1.s[0]
498 eor w8, w7, w7, ror #19
499 eor w8, w8, w7, ror #9
500 mov w7, v5.s[0]
[all …]
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| H A D | ghash-ce-core_a64.S | 482 cmp w7, #12
595 4: load_round_keys w7, x6
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| /optee_os/core/arch/arm/kernel/ |
| H A D | cache_helpers_a64.S | 133 lsl w7, w6, w2 // w7 = aligned max set number
136 orr w11, w9, w7 // combine cache, way and set number
138 subs w7, w7, w17 // decrement set number
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| H A D | thread_spmc_a64.S | 176 mov w7, w0 /* Supply thread index */
221 mov w7, w0
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| /optee_os/core/lib/libtomcrypt/src/stream/sosemanuk/ |
| H A D | sosemanuk.c | 235 WUP(w0, w3, w5, w7, cc); \ in sosemanuk_setup()
237 WUP(w2, w5, w7, w1, cc + 2); \ in sosemanuk_setup()
242 WUP(w4, w7, w1, w3, cc); \ in sosemanuk_setup()
245 WUP(w7, w2, w4, w6, cc + 3); \ in sosemanuk_setup()
249 ulong32 w0, w1, w2, w3, w4, w5, w6, w7; in sosemanuk_setup() local
275 LOAD32L(w7, wbuf + 28); in sosemanuk_setup()
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| /optee_os/core/drivers/crypto/hisilicon/ |
| H A D | hisi_qm.h | 129 uint16_t w7; member
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| H A D | hisi_qm.c | 81 #define QM_CQE_PHASE(cqe) (((cqe)->w7) & QM_FVT_CFG_RDY_BIT)
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