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Searched refs:AT91_PMC_PLL_CTRL1 (Results 1 – 3 of 3) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dclk-sam9x60-pll.c105 val = io_read32(regmap + AT91_PMC_PLL_CTRL1); in sam9x60_frac_pll_set()
120 io_write32(regmap + AT91_PMC_PLL_CTRL1, in sam9x60_frac_pll_set()
241 io_write32(regmap + AT91_PMC_PLL_CTRL1, in sam9x60_frac_pll_set_rate_chg()
442 val = io_read32(pmc->base + AT91_PMC_PLL_CTRL1); in sam9x60_clk_register_frac_pll()
H A Dat91_pmc.h46 #define AT91_PMC_PLL_CTRL1 0x10 macro
/optee_os/core/drivers/pm/sam/
H A Dpm_suspend.S686 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
750 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
754 str tmp1, [pmc, #AT91_PMC_PLL_CTRL1]