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Searched refs:tWB_max (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dnand_timings.c60 .tWB_max = 200000,
105 .tWB_max = 100000,
149 .tWB_max = 100000,
195 .tWB_max = 100000,
240 .tWB_max = 100000,
285 .tWB_max = 100000,
332 .tWB_max = 100000,
374 .tWB_max = 100000,
416 .tWB_max = 100000,
458 .tWB_max = 100000,
[all …]
H A Dnand_base.c619 ndelay(PSEC_TO_NSEC(timings->tWB_max)); in nand_soft_waitrdy()
1015 NAND_OP_ADDR(3, addrs, PSEC_TO_NSEC(sdr->tWB_max)), in nand_sp_exec_read_page_op()
1058 NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)), in nand_lp_exec_read_page_op()
1153 NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)), in nand_read_param_page_op()
1293 NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)), in nand_exec_prog_page_op()
1407 PSEC_TO_NSEC(sdr->tWB_max)), in nand_prog_page_end_op()
1680 PSEC_TO_MSEC(sdr->tWB_max)), in nand_erase_op()
1738 PSEC_TO_NSEC(sdr->tWB_max)), in nand_set_features_op()
1783 NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)), in nand_get_features_op()
1839 NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)), in nand_reset_op()
H A Dstm32_fmc2_nand.c1281 ndelay(PSEC_TO_NSEC(timings->tWB_max)); in stm32_fmc2_nfc_waitrdy()
1497 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && in stm32_fmc2_nfc_calc_timings()
1498 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) in stm32_fmc2_nfc_calc_timings()
1499 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; in stm32_fmc2_nfc_calc_timings()
H A Dsunxi_nand.c1454 if (timings->tWB_max > (min_clk_period * 20)) in sunxi_nfc_setup_interface()
1455 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20); in sunxi_nfc_setup_interface()
1480 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, in sunxi_nfc_setup_interface()
H A Dtango_nand.c533 Textw = to_ticks(kHz, sdr->tWB_max); in tango_set_timings()
H A Dtegra_nand.c802 reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1)); in tegra_nand_setup_timing()
H A Dmarvell_nand.c2408 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); in marvell_nfc_setup_interface()
2410 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, in marvell_nfc_setup_interface()
H A Dmeson_nand.c1122 meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max), in meson_nfc_setup_interface()
H A Dcadence-nand-controller.c2494 twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period); in cadence_nand_setup_interface()
/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Dnand_timings.c50 .tWB_max = 200000,
92 .tWB_max = 100000,
133 .tWB_max = 100000,
176 .tWB_max = 100000,
218 .tWB_max = 100000,
260 .tWB_max = 100000,
H A Dstm32_fmc2_nand.c759 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && in stm32_fmc2_calc_timings()
760 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) in stm32_fmc2_calc_timings()
761 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; in stm32_fmc2_calc_timings()
H A Dsunxi_nand.c1291 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, in sunxi_nand_chip_set_timings()
/OK3568_Linux_fs/kernel/include/linux/mtd/
H A Drawnand.h469 u32 tWB_max; member
557 u32 tWB_max; member
/OK3568_Linux_fs/u-boot/include/linux/mtd/
H A Drawnand.h714 u32 tWB_max; member
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1448 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()