Searched refs:pdiv2 (Results 1 – 4 of 4) sorted by relevance
238 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local247 for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) { in calc_pll()248 postdiv = pdiv1 * pdiv2; in calc_pll()266 par->pll_pd2 = pdiv2; in calc_pll()
37 u32 pdiv2; member
96 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2); in setup_clock_synthesizer()
605 .pdiv2 = 0x2,674 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ in board_init()