| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v3_0.c | 83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
1448 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
1458 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
[all …]
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| H A D | mxgpu_vi.c | 92 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
223 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
244 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
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| H A D | cik_sdma.c | 887 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
888 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
890 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
893 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
895 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
898 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
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| H A D | sdma_v4_0.c | 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
2160 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); in sdma_v4_0_update_medium_grain_clock_gating()
2170 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); in sdma_v4_0_update_medium_grain_clock_gating()
2174 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); in sdma_v4_0_update_medium_grain_clock_gating()
2184 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); in sdma_v4_0_update_medium_grain_clock_gating()
2269 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_get_clockgating_state()
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| H A D | sdma_v5_0.c | 1507 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_0_update_medium_grain_clock_gating()
1517 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_0_update_medium_grain_clock_gating()
1520 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_0_update_medium_grain_clock_gating()
1530 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_0_update_medium_grain_clock_gating()
1599 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); in sdma_v5_0_get_clockgating_state()
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| H A D | sdma_v5_2.c | 1505 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_2_update_medium_grain_clock_gating()
1513 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_2_update_medium_grain_clock_gating()
1516 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_2_update_medium_grain_clock_gating()
1524 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_2_update_medium_grain_clock_gating()
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| H A D | sdma_v2_4.c | 69 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
76 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 66 #define mmSDMA0_CLK_CTRL … macro
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| H A D | sdma0_4_0_offset.h | 68 #define mmSDMA0_CLK_CTRL 0x001b macro
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| H A D | sdma0_4_2_offset.h | 68 #define mmSDMA0_CLK_CTRL … macro
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| H A D | sdma0_4_2_2_offset.h | 68 #define mmSDMA0_CLK_CTRL … macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 160 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| H A D | oss_3_0_1_d.h | 157 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| H A D | oss_2_0_d.h | 222 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| H A D | oss_3_0_d.h | 294 #define mmSDMA0_CLK_CTRL 0x3403 macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 43 #define mmSDMA0_CLK_CTRL … macro
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| H A D | gc_10_3_0_offset.h | 48 #define mmSDMA0_CLK_CTRL … macro
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