Home
last modified time | relevance | path

Searched refs:hw_cfg (Results 1 – 19 of 19) sorted by relevance

/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu1_v2.c40 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg; in vp8e_vpu_frame_start() local
45 regs->sw1.val = hw_cfg->irq_disable ? (regs->sw1.val | 0x02) : in vp8e_vpu_frame_start()
49 if (hw_cfg->input_format < INPUT_RGB565) in vp8e_vpu_frame_start()
52 else if (hw_cfg->input_format < INPUT_RGB888) in vp8e_vpu_frame_start()
57 regs->sw5.base_stream = hw_cfg->output_strm_base; in vp8e_vpu_frame_start()
58 mpp_dev_set_reg_offset(ctx->dev, 5, hw_cfg->output_strm_offset); in vp8e_vpu_frame_start()
60 regs->sw6.base_control = hw_cfg->size_tbl_base; in vp8e_vpu_frame_start()
61 regs->sw14.nal_size_write = (hw_cfg->size_tbl_base != 0); in vp8e_vpu_frame_start()
62 regs->sw14.mv_write = (hw_cfg->mv_output_base != 0); in vp8e_vpu_frame_start()
64 regs->sw7.base_ref_lum = hw_cfg->internal_img_lum_base_r[0]; in vp8e_vpu_frame_start()
[all …]
H A Dhal_vp8e_vepu2_v2.c41 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg; in vp8e_vpu_frame_start() local
46 regs->sw109.val = hw_cfg->irq_disable ? (regs->sw109.val | 0x0100) : in vp8e_vpu_frame_start()
52 if (hw_cfg->input_format < INPUT_RGB565) { in vp8e_vpu_frame_start()
54 } else if (hw_cfg->input_format < INPUT_RGB888) { in vp8e_vpu_frame_start()
60 regs->sw77.base_stream = hw_cfg->output_strm_base; in vp8e_vpu_frame_start()
61 mpp_dev_set_reg_offset(ctx->dev, 77, hw_cfg->output_strm_offset); in vp8e_vpu_frame_start()
62 regs->sw78.base_control = hw_cfg->size_tbl_base; in vp8e_vpu_frame_start()
63 regs->sw74.nal_size_write = hw_cfg->size_tbl_base != 0; in vp8e_vpu_frame_start()
64 regs->sw109.mv_write = hw_cfg->mv_output_base != 0; in vp8e_vpu_frame_start()
66 regs->sw56.base_ref_lum = hw_cfg->internal_img_lum_base_r[0]; in vp8e_vpu_frame_start()
[all …]
H A Dhal_vp8e_base.c129 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg; in set_segmentation() local
135 if (hw_cfg->roi1_delta_qp) in set_segmentation()
136 pps->qp_sgm[1] = MPP_CLIP3(0, 127, qp - hw_cfg->roi1_delta_qp); in set_segmentation()
138 if (hw_cfg->roi2_delta_qp) in set_segmentation()
139 pps->qp_sgm[2] = MPP_CLIP3(0, 127, qp - hw_cfg->roi2_delta_qp); in set_segmentation()
148 if (hw_cfg->roi1_delta_qp || hw_cfg->roi2_delta_qp) { in set_segmentation()
156 if ((x >= hw_cfg->roi1_left) && (x <= hw_cfg->roi1_right) && in set_segmentation()
157 (y >= hw_cfg->roi1_top) && (y <= hw_cfg->roi1_bottom)) in set_segmentation()
159 if ((x >= hw_cfg->roi1_left) && (x <= hw_cfg->roi2_right) && in set_segmentation()
160 (y >= hw_cfg->roi2_top) && (y <= hw_cfg->roi2_bottom)) in set_segmentation()
[all …]
H A Dhal_vp8e_base.h347 Vp8eHwCfg hw_cfg; member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_kms.c355 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) in get_dsi_id_from_intf() argument
357 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; in get_dsi_id_from_intf()
358 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); in get_dsi_id_from_intf()
422 const struct mdp5_cfg_hw *hw_cfg = in modeset_init_intf() local
424 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); in modeset_init_intf()
735 const struct mdp5_cfg_hw *hw_cfg; in hwpipe_init() local
738 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); in hwpipe_init()
741 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, in hwpipe_init()
742 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); in hwpipe_init()
747 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, in hwpipe_init()
[all …]
H A Dmdp5_ctl.c684 const struct mdp5_cfg_hw *hw_cfg = mdp5_cfg_get_hw_config(cfg_hnd); in mdp5_ctlm_init() local
687 const struct mdp5_ctl_block *ctl_cfg = &hw_cfg->ctl; in mdp5_ctlm_init()
707 ctl_mgr->nlm = hw_cfg->lm.count; in mdp5_ctlm_init()
736 for (c = 0; c < ARRAY_SIZE(hw_cfg->intf.connect); c++) in mdp5_ctlm_init()
737 if (hw_cfg->intf.connect[c] == INTF_DSI) in mdp5_ctlm_init()
H A Dmdp5_crtc.c697 const struct mdp5_cfg_hw *hw_cfg; in mdp5_crtc_atomic_check() local
731 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); in mdp5_crtc_atomic_check()
737 if (mode->hdisplay > hw_cfg->lm.max_width) in mdp5_crtc_atomic_check()
758 if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) { in mdp5_crtc_atomic_check()
766 pstates[i].state->stage = hw_cfg->lm.nb_stages; in mdp5_crtc_atomic_check()
/OK3568_Linux_fs/kernel/drivers/video/rockchip/mpp/
H A Dmpp_iep2.c504 struct iep2_params *hw_cfg = &task->params; in iep2_osd_cfg() local
508 for (i = 0; i < hw_cfg->osd_area_num; ++i) { in iep2_osd_cfg()
509 reg = IEP2_REG_OSD_X_STA(hw_cfg->osd_x_sta[i]) in iep2_osd_cfg()
510 | IEP2_REG_OSD_X_END(hw_cfg->osd_x_end[i]) in iep2_osd_cfg()
511 | IEP2_REG_OSD_Y_STA(hw_cfg->osd_y_sta[i]) in iep2_osd_cfg()
512 | IEP2_REG_OSD_Y_END(hw_cfg->osd_y_end[i]); in iep2_osd_cfg()
516 for (; i < ARRAY_SIZE(hw_cfg->osd_x_sta); ++i) in iep2_osd_cfg()
522 struct iep2_params *hw_cfg = &task->params; in iep2_mtn_tab_cfg() local
524 u32 *mtn_tab = hw_cfg->mtn_en ? hw_cfg->mtn_tab : iep2_mtn_tab; in iep2_mtn_tab_cfg()
526 for (i = 0; i < ARRAY_SIZE(hw_cfg->mtn_tab); ++i) in iep2_mtn_tab_cfg()
[all …]
/OK3568_Linux_fs/external/mpp/mpp/hal/common/h264/
H A Dhal_h264e_stream_amend.c99 MppEncH264HwCfg *hw_cfg = &h264->hw_cfg; in h264e_vepu_stream_amend_config() local
102 hw_cfg->hw_poc_type != h264->poc_type || in h264e_vepu_stream_amend_config()
103 hw_cfg->hw_log2_max_frame_num_minus4 != h264->log2_max_frame_num) { in h264e_vepu_stream_amend_config()
132 MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx, MppEncH264HwCfg *hw_cfg) in h264e_vepu_stream_amend_proc() argument
223 slice_rd.pic_order_cnt_type = hw_cfg->hw_poc_type; in h264e_vepu_stream_amend_proc()
224 slice_rd.log2_max_frame_num = hw_cfg->hw_log2_max_frame_num_minus4 + 4; in h264e_vepu_stream_amend_proc()
H A Dhal_h264e_stream_amend.h49 MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx, MppEncH264HwCfg *hw_cfg);
/OK3568_Linux_fs/external/mpp/mpp/codec/enc/h264/
H A Dh264e_api_v2.c110 h264->hw_cfg.hw_poc_type = 2; in init_h264e_cfg_set()
111 h264->hw_cfg.hw_log2_max_frame_num_minus4 = 12; in init_h264e_cfg_set()
119 h264->hw_cfg.hw_poc_type = 0; in init_h264e_cfg_set()
120 h264->hw_cfg.hw_log2_max_frame_num_minus4 = 12; in init_h264e_cfg_set()
126 h264->hw_cfg.hw_poc_type = 0; in init_h264e_cfg_set()
127 h264->hw_cfg.hw_log2_max_frame_num_minus4 = 12; in init_h264e_cfg_set()
H A Dh264e_sps.c164 sps->pic_order_cnt_type = h264->hw_cfg.hw_poc_type; in h264e_sps_update()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/atheros/alx/
H A Dhw.c853 u32 cfg, hw_cfg; in alx_phy_configured() local
857 hw_cfg = alx_get_phy_config(hw); in alx_phy_configured()
859 if (hw_cfg == ALX_DRV_PHY_UNKNOWN) in alx_phy_configured()
862 return cfg == hw_cfg; in alx_phy_configured()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu_v2.c516 MppEncHwCfg* hw_cfg = &cfg->hw; in h264e_vepu_mbrc_setup() local
545 p->mb_bit_rc_enable = !hw_cfg->mb_rc_disable && (rc->rc_mode != MPP_ENC_RC_MODE_FIXQP); in h264e_vepu_mbrc_setup()
H A Dhal_h264e_vepu1_v2.c676 h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg); in hal_h264e_vepu1_wait_v2()
H A Dhal_h264e_vepu2_v2.c741 h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg); in hal_h264e_vepu2_wait_v2()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c340 MppEncH264HwCfg *hw_cfg = &ctx->cfg->codec.h264.hw_cfg; in hal_h264e_vepu541_get_task() local
360 hw_cfg->hw_log2_max_frame_num_minus4 = ctx->sps->log2_max_frame_num_minus4; in hal_h264e_vepu541_get_task()
1741 h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg); in hal_h264e_vepu541_wait()
H A Dhal_h264e_vepu580.c548 MppEncH264HwCfg *hw_cfg = &cfg_set->codec.h264.hw_cfg; in hal_h264e_vepu580_get_task() local
583 hw_cfg->hw_log2_max_frame_num_minus4 = ctx->sps->log2_max_frame_num_minus4; in hal_h264e_vepu580_get_task()
2513 h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg); in hal_h264e_vepu580_wait()
/OK3568_Linux_fs/external/mpp/inc/
H A Drk_venc_cmd.h732 MppEncH264HwCfg hw_cfg; member