| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/ |
| H A D | halbb_plcp_tx.c | 157 struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; in halbb_plcp_lsig() local
203 halbb_set_reg_cmn(bb, cr->lsig, cr->lsig_m, lsig, phy_idx); in halbb_plcp_lsig()
217 struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; in halbb_plcp_siga() local
405 halbb_set_reg_cmn(bb, cr->siga1, cr->siga1_m, siga1, phy_idx); in halbb_plcp_siga()
406 halbb_set_reg_cmn(bb, cr->siga2, cr->siga2_m, siga2, phy_idx); in halbb_plcp_siga()
417 struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; in halbb_cfg_txinfo() local
421 halbb_set_reg_cmn(bb, cr->cfo_comp, cr->cfo_comp_m, 7, phy_idx); in halbb_cfg_txinfo()
422 halbb_set_reg_cmn(bb, cr->obw_cts2self_dup_type, cr->obw_cts2self_dup_type_m, 0, phy_idx); in halbb_cfg_txinfo()
423 halbb_set_reg_cmn(bb, cr->txcmd_txtp, cr->txcmd_txtp_m, 0, phy_idx); in halbb_cfg_txinfo()
424 halbb_set_reg_cmn(bb, cr->ul_cqi_rpt_tri, cr->ul_cqi_rpt_tri_m, 0, phy_idx); in halbb_cfg_txinfo()
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| H A D | halbb_mp.c | 32 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_tx_ok() local
35 tx_ok = halbb_get_reg(bb, cr->cnt_ccktxon, cr->cnt_ccktxon_m); in halbb_mp_get_tx_ok()
37 tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx); in halbb_mp_get_tx_ok()
46 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_rx_crc_ok() local
49 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p0, cr->cnt_cck_crc32ok_p0_m); in halbb_mp_get_rx_crc_ok()
51 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p1, cr->cnt_cck_crc32ok_p1_m); in halbb_mp_get_rx_crc_ok()
53 ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
54 ht_ok = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_ok, cr->cnt_ht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
55 vht_ok = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_ok, cr->cnt_vht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
56 he_ok = halbb_get_reg_cmn(bb, cr->cnt_he_crc_ok, cr->cnt_he_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
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| H A D | halbb_statistics.c | 33 struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; in halbb_set_crc32_cnt2_rate() local
38 u32 reg_addr = cr->intf_r_rate; in halbb_set_crc32_cnt2_rate()
39 u32 ofdm_rate_bitmask = cr->intf_r_rate_m; in halbb_set_crc32_cnt2_rate()
40 u32 ht_mcs_bitmask = cr->intf_r_mcs_m; in halbb_set_crc32_cnt2_rate()
41 u32 vht_mcs_bitmask = cr->intf_r_vht_mcs_m; in halbb_set_crc32_cnt2_rate()
42 u32 vht_ss_bitmask = cr->intf_r_vht_nss_m; in halbb_set_crc32_cnt2_rate()
43 u32 he_mcs_bitmask =cr->intf_r_he_mcs_m; in halbb_set_crc32_cnt2_rate()
44 u32 he_ss_bitmask = cr->intf_r_he_nss_m; in halbb_set_crc32_cnt2_rate()
96 struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; in halbb_set_crc32_cnt3_format() local
97 u32 reg_addr = cr->intf_r_mac_hdr_type; in halbb_set_crc32_cnt3_format()
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| H A D | halbb_la_mode.c | 344 struct bb_la_cr_info *cr = &la->bb_la_cr_i; in halbb_la_mac_set_trig() local
350 halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m, 0); in halbb_la_mac_set_trig()
352 halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m, 0); in halbb_la_mac_set_trig()
354 halbb_set_reg(bb, cr->la_mac_and2_en, cr->la_mac_and2_en_m, 0); in halbb_la_mac_set_trig()
358 halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m, in halbb_la_mac_set_trig()
360 halbb_set_reg(bb, cr->la_mac_and0_sel, cr->la_mac_and0_sel_m, in halbb_la_mac_set_trig()
362 halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(16), 0); in halbb_la_mac_set_trig()
364 halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(22), in halbb_la_mac_set_trig()
367 halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(23), in halbb_la_mac_set_trig()
369 halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m, in halbb_la_mac_set_trig()
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| H A D | halbb_env_mntr.c | 91 struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; in halbb_ccx_top_setting_init() local
102 halbb_set_reg_phy0_1(bb, cr->ccx_en, cr->ccx_en_m, 1); in halbb_ccx_top_setting_init()
103 halbb_set_reg_phy0_1(bb, cr->ccx_trig_opt, cr->ccx_trig_opt_m, 1); in halbb_ccx_top_setting_init()
104 halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1); in halbb_ccx_top_setting_init()
105 halbb_set_reg_phy0_1(bb, cr->ccx_edcca_opt, cr->ccx_edcca_opt_m, in halbb_ccx_top_setting_init()
155 struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; in halbb_ccx_trigger() local
160 halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 0); in halbb_ccx_trigger()
161 halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 0); in halbb_ccx_trigger()
162 halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 1); in halbb_ccx_trigger()
163 halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1); in halbb_ccx_trigger()
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| H A D | halbb_dig.c | 387 const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; in halbb_get_lna_idx() local
393 lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_lna_init_idx, in halbb_get_lna_idx()
394 cr->path0_lna_init_idx_m, in halbb_get_lna_idx()
398 lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_lna_init_idx, in halbb_get_lna_idx()
399 cr->path1_lna_init_idx_m, in halbb_get_lna_idx()
412 const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; in halbb_get_tia_idx() local
417 tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_tia_init_idx, in halbb_get_tia_idx()
418 cr->path0_tia_init_idx_m, in halbb_get_tia_idx()
422 tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_tia_init_idx, in halbb_get_tia_idx()
423 cr->path1_tia_init_idx_m, in halbb_get_tia_idx()
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| H A D | halbb_edcca.c | 46 struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; in halbb_set_edcca_thre() local
49 halbb_set_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m, l2h); in halbb_set_edcca_thre()
50 halbb_set_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m, l2h); in halbb_set_edcca_thre()
52 halbb_set_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m, (u32)bb_edcca->th_hl_diff); in halbb_set_edcca_thre()
134 struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; in halbb_edcca_log() local
189 edcca_en = (bool)halbb_get_reg(bb, cr->r_snd_en, cr->r_snd_en_m); in halbb_edcca_log()
190 edcca_p_th = (u8)halbb_get_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m); in halbb_edcca_log()
191 edcca_s_th = (u8)halbb_get_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m); in halbb_edcca_log()
192 edcca_diff = (u8)halbb_get_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m); in halbb_edcca_log()
203 struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; in halbb_edcca_get_result() local
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| H A D | halbb_ant_div.c | 58 struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; in halbb_antdiv_reg_init() local
61 halbb_set_reg_cmn(bb, cr->path0_r_ant_train_en, cr->path0_r_ant_train_en_m, 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
64 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(1), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
79 …halbb_set_reg_cmn(bb, cr->path0_r_bt_force_antidx_en, cr->path0_r_bt_force_antidx_en_m, 0x0, HW_PH… in halbb_antdiv_reg_init()
82 halbb_set_reg_cmn(bb, cr->path0_r_rfsw_ant_31_0, 0xFFFF, 0x0100, HW_PHY_0); in halbb_antdiv_reg_init()
85 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(21), 0x1, HW_PHY_0); in halbb_antdiv_reg_init()
88 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(16), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
90 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(23), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
92 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(25), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
169 struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; in halbb_antdiv_set_ant() local
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/ |
| H A D | halbb_plcp_tx.c | 157 struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; in halbb_plcp_lsig() local
203 halbb_set_reg_cmn(bb, cr->lsig, cr->lsig_m, lsig, phy_idx); in halbb_plcp_lsig()
217 struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; in halbb_plcp_siga() local
405 halbb_set_reg_cmn(bb, cr->siga1, cr->siga1_m, siga1, phy_idx); in halbb_plcp_siga()
406 halbb_set_reg_cmn(bb, cr->siga2, cr->siga2_m, siga2, phy_idx); in halbb_plcp_siga()
417 struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; in halbb_cfg_txinfo() local
421 halbb_set_reg_cmn(bb, cr->cfo_comp, cr->cfo_comp_m, 7, phy_idx); in halbb_cfg_txinfo()
422 halbb_set_reg_cmn(bb, cr->obw_cts2self_dup_type, cr->obw_cts2self_dup_type_m, 0, phy_idx); in halbb_cfg_txinfo()
423 halbb_set_reg_cmn(bb, cr->txcmd_txtp, cr->txcmd_txtp_m, 0, phy_idx); in halbb_cfg_txinfo()
424 halbb_set_reg_cmn(bb, cr->ul_cqi_rpt_tri, cr->ul_cqi_rpt_tri_m, 0, phy_idx); in halbb_cfg_txinfo()
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| H A D | halbb_mp.c | 32 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_tx_ok() local
35 tx_ok = halbb_get_reg(bb, cr->cnt_ccktxon, cr->cnt_ccktxon_m); in halbb_mp_get_tx_ok()
37 tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx); in halbb_mp_get_tx_ok()
46 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_rx_crc_ok() local
49 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p0, cr->cnt_cck_crc32ok_p0_m); in halbb_mp_get_rx_crc_ok()
51 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p1, cr->cnt_cck_crc32ok_p1_m); in halbb_mp_get_rx_crc_ok()
53 ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
54 ht_ok = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_ok, cr->cnt_ht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
55 vht_ok = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_ok, cr->cnt_vht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
56 he_ok = halbb_get_reg_cmn(bb, cr->cnt_he_crc_ok, cr->cnt_he_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
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| H A D | halbb_statistics.c | 33 struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; in halbb_set_crc32_cnt2_rate() local
38 u32 reg_addr = cr->intf_r_rate; in halbb_set_crc32_cnt2_rate()
39 u32 ofdm_rate_bitmask = cr->intf_r_rate_m; in halbb_set_crc32_cnt2_rate()
40 u32 ht_mcs_bitmask = cr->intf_r_mcs_m; in halbb_set_crc32_cnt2_rate()
41 u32 vht_mcs_bitmask = cr->intf_r_vht_mcs_m; in halbb_set_crc32_cnt2_rate()
42 u32 vht_ss_bitmask = cr->intf_r_vht_nss_m; in halbb_set_crc32_cnt2_rate()
43 u32 he_mcs_bitmask =cr->intf_r_he_mcs_m; in halbb_set_crc32_cnt2_rate()
44 u32 he_ss_bitmask = cr->intf_r_he_nss_m; in halbb_set_crc32_cnt2_rate()
96 struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; in halbb_set_crc32_cnt3_format() local
97 u32 reg_addr = cr->intf_r_mac_hdr_type; in halbb_set_crc32_cnt3_format()
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| H A D | halbb_la_mode.c | 344 struct bb_la_cr_info *cr = &la->bb_la_cr_i; in halbb_la_mac_set_trig() local
350 halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m, 0); in halbb_la_mac_set_trig()
352 halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m, 0); in halbb_la_mac_set_trig()
354 halbb_set_reg(bb, cr->la_mac_and2_en, cr->la_mac_and2_en_m, 0); in halbb_la_mac_set_trig()
358 halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m, in halbb_la_mac_set_trig()
360 halbb_set_reg(bb, cr->la_mac_and0_sel, cr->la_mac_and0_sel_m, in halbb_la_mac_set_trig()
362 halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(16), 0); in halbb_la_mac_set_trig()
364 halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(22), in halbb_la_mac_set_trig()
367 halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(23), in halbb_la_mac_set_trig()
369 halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m, in halbb_la_mac_set_trig()
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| H A D | halbb_env_mntr.c | 91 struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; in halbb_ccx_top_setting_init() local
102 halbb_set_reg_phy0_1(bb, cr->ccx_en, cr->ccx_en_m, 1); in halbb_ccx_top_setting_init()
103 halbb_set_reg_phy0_1(bb, cr->ccx_trig_opt, cr->ccx_trig_opt_m, 1); in halbb_ccx_top_setting_init()
104 halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1); in halbb_ccx_top_setting_init()
105 halbb_set_reg_phy0_1(bb, cr->ccx_edcca_opt, cr->ccx_edcca_opt_m, in halbb_ccx_top_setting_init()
155 struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; in halbb_ccx_trigger() local
160 halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 0); in halbb_ccx_trigger()
161 halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 0); in halbb_ccx_trigger()
162 halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 1); in halbb_ccx_trigger()
163 halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1); in halbb_ccx_trigger()
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| H A D | halbb_dig.c | 387 const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; in halbb_get_lna_idx() local
393 lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_lna_init_idx, in halbb_get_lna_idx()
394 cr->path0_lna_init_idx_m, in halbb_get_lna_idx()
398 lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_lna_init_idx, in halbb_get_lna_idx()
399 cr->path1_lna_init_idx_m, in halbb_get_lna_idx()
412 const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; in halbb_get_tia_idx() local
417 tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_tia_init_idx, in halbb_get_tia_idx()
418 cr->path0_tia_init_idx_m, in halbb_get_tia_idx()
422 tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_tia_init_idx, in halbb_get_tia_idx()
423 cr->path1_tia_init_idx_m, in halbb_get_tia_idx()
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| H A D | halbb_edcca.c | 46 struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; in halbb_set_edcca_thre() local
49 halbb_set_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m, l2h); in halbb_set_edcca_thre()
50 halbb_set_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m, l2h); in halbb_set_edcca_thre()
52 halbb_set_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m, (u32)bb_edcca->th_hl_diff); in halbb_set_edcca_thre()
134 struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; in halbb_edcca_log() local
189 edcca_en = (bool)halbb_get_reg(bb, cr->r_snd_en, cr->r_snd_en_m); in halbb_edcca_log()
190 edcca_p_th = (u8)halbb_get_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m); in halbb_edcca_log()
191 edcca_s_th = (u8)halbb_get_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m); in halbb_edcca_log()
192 edcca_diff = (u8)halbb_get_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m); in halbb_edcca_log()
203 struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; in halbb_edcca_get_result() local
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| H A D | halbb_ant_div.c | 58 struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; in halbb_antdiv_reg_init() local
61 halbb_set_reg_cmn(bb, cr->path0_r_ant_train_en, cr->path0_r_ant_train_en_m, 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
64 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(1), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
79 …halbb_set_reg_cmn(bb, cr->path0_r_bt_force_antidx_en, cr->path0_r_bt_force_antidx_en_m, 0x0, HW_PH… in halbb_antdiv_reg_init()
82 halbb_set_reg_cmn(bb, cr->path0_r_rfsw_ant_31_0, 0xFFFF, 0x0100, HW_PHY_0); in halbb_antdiv_reg_init()
85 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(21), 0x1, HW_PHY_0); in halbb_antdiv_reg_init()
88 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(16), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
90 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(23), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
92 halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(25), 0x0, HW_PHY_0); in halbb_antdiv_reg_init()
169 struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; in halbb_antdiv_set_ant() local
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| H A D | halbb_dbg.c | 164 struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; in halbb_bb_dbg_port_clock_en() local
168 halbb_set_reg(bb, cr->clk_en, cr->clk_en_m, reg_value); in halbb_bb_dbg_port_clock_en()
169 halbb_set_reg(bb, cr->dbgport_en, cr->dbgport_en_m, reg_value); in halbb_bb_dbg_port_clock_en()
175 struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; in halbb_get_bb_dbg_port_idx() local
179 ip = halbb_get_reg(bb, cr->dbgport_ip, cr->dbgport_ip_m); in halbb_get_bb_dbg_port_idx()
180 dbg_port = halbb_get_reg(bb, cr->dbgport_idx, cr->dbgport_idx_m); in halbb_get_bb_dbg_port_idx()
189 struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; in halbb_set_bb_dbg_port_ip() local
191 halbb_set_reg(bb, cr->dbgport_ip, cr->dbgport_ip_m, ip); in halbb_set_bb_dbg_port_ip()
196 struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; in halbb_set_bb_dbg_port() local
198 halbb_set_reg(bb, cr->dbgport_idx, cr->dbgport_idx_m, dbg_port); in halbb_set_bb_dbg_port()
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| /OK3568_Linux_fs/kernel/drivers/target/iscsi/ |
| H A D | iscsi_target_erl2.c | 78 struct iscsi_conn_recovery *cr) in iscsit_attach_active_connection_recovery_entry() argument
81 list_add_tail(&cr->cr_list, &sess->cr_active_list); in iscsit_attach_active_connection_recovery_entry()
89 struct iscsi_conn_recovery *cr) in iscsit_attach_inactive_connection_recovery_entry() argument
92 list_add_tail(&cr->cr_list, &sess->cr_inactive_list); in iscsit_attach_inactive_connection_recovery_entry()
106 struct iscsi_conn_recovery *cr; in iscsit_get_inactive_connection_recovery_entry() local
109 list_for_each_entry(cr, &sess->cr_inactive_list, cr_list) { in iscsit_get_inactive_connection_recovery_entry()
110 if (cr->cid == cid) { in iscsit_get_inactive_connection_recovery_entry()
112 return cr; in iscsit_get_inactive_connection_recovery_entry()
123 struct iscsi_conn_recovery *cr, *cr_tmp; in iscsit_free_connection_recovery_entries() local
126 list_for_each_entry_safe(cr, cr_tmp, &sess->cr_active_list, cr_list) { in iscsit_free_connection_recovery_entries()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-imx/ |
| H A D | ddrmc-vf610.c | 117 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); in ddrmc_ctrl_init_ddr3()
118 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
119 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
121 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
123 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
127 &ddrmr->cr[13]); in ddrmc_ctrl_init_ddr3()
130 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]); in ddrmc_ctrl_init_ddr3()
132 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]); in ddrmc_ctrl_init_ddr3()
134 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]); in ddrmc_ctrl_init_ddr3()
136 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); in ddrmc_ctrl_init_ddr3()
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| /OK3568_Linux_fs/kernel/drivers/crypto/ccp/ |
| H A D | ccp-dev-v3.c | 74 static int ccp_do_cmd(struct ccp_op *op, u32 *cr, unsigned int cr_count) in ccp_do_cmd() argument
107 iowrite32(*(cr + i), cr_addr); in ccp_do_cmd()
150 u32 cr[6]; in ccp_perform_aes() local
153 cr[0] = (CCP_ENGINE_AES << REQ1_ENGINE_SHIFT) in ccp_perform_aes()
158 cr[1] = op->src.u.dma.length - 1; in ccp_perform_aes()
159 cr[2] = ccp_addr_lo(&op->src.u.dma); in ccp_perform_aes()
160 cr[3] = (op->sb_ctx << REQ4_KSB_SHIFT) in ccp_perform_aes()
163 cr[4] = ccp_addr_lo(&op->dst.u.dma); in ccp_perform_aes()
164 cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) in ccp_perform_aes()
168 cr[0] |= ((0x7f) << REQ1_AES_CFB_SIZE_SHIFT); in ccp_perform_aes()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-at91/ |
| H A D | mpddrc.c | 25 static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr) in ddr2_decodtype_is_seq() argument
31 (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) in ddr2_decodtype_is_seq()
44 u32 ba_off, cr; in ddr2_init() local
47 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; in ddr2_init()
48 if (ddr2_decodtype_is_seq(base, mpddr_value->cr)) in ddr2_init()
49 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; in ddr2_init()
57 writel(mpddr_value->cr, &mpddr->cr); in ddr2_init()
92 cr = readl(&mpddr->cr); in ddr2_init()
93 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); in ddr2_init()
106 cr = readl(&mpddr->cr); in ddr2_init()
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| /OK3568_Linux_fs/kernel/arch/s390/include/asm/ |
| H A D | ctl_reg.h | 59 static __always_inline void __ctl_set_bit(unsigned int cr, unsigned int bit) in __ctl_set_bit() argument
63 __ctl_store(reg, cr, cr); in __ctl_set_bit()
65 __ctl_load(reg, cr, cr); in __ctl_set_bit()
68 static __always_inline void __ctl_clear_bit(unsigned int cr, unsigned int bit) in __ctl_clear_bit() argument
72 __ctl_store(reg, cr, cr); in __ctl_clear_bit()
74 __ctl_load(reg, cr, cr); in __ctl_clear_bit()
77 void smp_ctl_set_bit(int cr, int bit);
78 void smp_ctl_clear_bit(int cr, int bit);
116 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit) argument
117 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit) argument
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| /OK3568_Linux_fs/kernel/arch/parisc/include/asm/ |
| H A D | special_insns.h | 34 unsigned long cr; \
37 "=r" (cr) \
39 cr; \
42 #define mtctl(gr, cr) \ argument
45 : "r" (gr), "i" (cr) : "memory")
56 unsigned long cr; \
59 "=r" (cr) \
61 cr; \
64 #define mtsp(val, cr) \ argument
66 __asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \
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| /OK3568_Linux_fs/kernel/drivers/misc/cxl/ |
| H A D | sysfs.c | 508 int cr; member
519 struct afu_config_record *cr = to_cr(kobj); in vendor_show() local
521 return scnprintf(buf, PAGE_SIZE, "0x%.4x\n", cr->vendor); in vendor_show()
527 struct afu_config_record *cr = to_cr(kobj); in device_show() local
529 return scnprintf(buf, PAGE_SIZE, "0x%.4x\n", cr->device); in device_show()
535 struct afu_config_record *cr = to_cr(kobj); in class_show() local
537 return scnprintf(buf, PAGE_SIZE, "0x%.6x\n", cr->class); in class_show()
544 struct afu_config_record *cr = to_cr(kobj); in afu_read_config() local
550 rc = cxl_ops->afu_cr_read64(afu, cr->cr, off & ~0x7, &val); in afu_read_config()
576 struct afu_config_record *cr = to_cr(kobj); in release_afu_config_record() local
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| /OK3568_Linux_fs/kernel/drivers/clocksource/ |
| H A D | timer-fttmr010.c | 146 u32 cr; in fttmr010_timer_set_next_event() local
159 cr = readl(fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_next_event()
160 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
164 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
165 cr |= fttmr010->t1_enable_val; in fttmr010_timer_set_next_event()
166 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
184 u32 cr; in fttmr010_timer_shutdown() local
187 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
188 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_shutdown()
189 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
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