Searched refs:apllcsr (Results 1 – 2 of 2) sorted by relevance
512 reg = readl(&scg1_regs->apllcsr); in decode_pll()964 val = readl(&scg1_regs->apllcsr); in scg_a7_apll_init()966 writel(val, &scg1_regs->apllcsr); in scg_a7_apll_init()978 val = readl(&scg1_regs->apllcsr); in scg_a7_apll_init()980 writel(val, &scg1_regs->apllcsr); in scg_a7_apll_init()983 while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK)) in scg_a7_apll_init()
300 u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */ member