Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL (Results 1 – 1 of 1) sorted by relevance
187 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4) macro226 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136); in pcie_phy_enable()