Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV (Results 1 – 1 of 1) sorted by relevance
176 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20) macro256 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25); in pcie_phy_enable()