Searched refs:UNIPHIER_SD_CLKCTL_DIV4 (Results 1 – 1 of 1) sorted by relevance
73 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ macro558 val = UNIPHIER_SD_CLKCTL_DIV4; in uniphier_sd_set_clk_rate()