Searched refs:TRCVISSCTLR (Results 1 – 3 of 3) sorted by relevance
92 WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCVISSCTLR, 0x00000000),
43 #define TRCVISSCTLR 0x088 macro197 CASE_##op((val), TRCVISSCTLR) \
420 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); in etm4_enable_hw()1617 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); in __etm4_cpu_save()1746 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); in __etm4_cpu_restore()