Searched refs:TRCEVENTCTL1R (Results 1 – 3 of 3) sorted by relevance
74 WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCEVENTCTL1R, 0x00000000),
31 #define TRCEVENTCTL1R 0x024 macro187 CASE_##op((val), TRCEVENTCTL1R) \
410 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); in etm4_enable_hw()1605 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); in __etm4_cpu_save()1734 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); in __etm4_cpu_restore()