Searched refs:TRCEVENTCTL0R (Results 1 – 3 of 3) sorted by relevance
72 WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCEVENTCTL0R, 0x00000000),
30 #define TRCEVENTCTL0R 0x020 macro186 CASE_##op((val), TRCEVENTCTL0R) \
409 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); in etm4_enable_hw()1604 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); in __etm4_cpu_save()1733 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); in __etm4_cpu_restore()