Searched refs:TEGRA20_CLK_PLL_D_OUT0 (Results 1 – 7 of 7) sorted by relevance
139 #define TEGRA20_CLK_PLL_D_OUT0 117 macro
140 #define TEGRA20_CLK_PLL_D_OUT0 117 macro
344 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;363 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
430 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },673 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; in tegra20_pll_init()
141 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;160 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
526 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;545 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
118 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;