Searched refs:SOC_CORE_CLK_CTRL_DIV_MASK (Results 1 – 2 of 2) sorted by relevance
801 reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK; in ath10k_hw_qca6174_enable_pll_clock()
1171 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 macro