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Searched refs:REG_TRAINING_DEBUG_3_OFFS (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c346 reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS); in ddr3_init()
347 reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */ in ddr3_init()
348 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init()
349 reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */ in ddr3_init()
350 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init()
351 reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init()
352 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init()
353 reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init()
H A Dddr3_hws_hw_training_def.h220 #define REG_TRAINING_DEBUG_3_OFFS 3 macro
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c516 reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS); in ddr3_init_main()
517 reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */ in ddr3_init_main()
518 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()
519 reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */ in ddr3_init_main()
520 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()
521 reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()
522 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()
523 reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()
H A Dddr3_read_leveling.c663 REG_TRAINING_DEBUG_3_OFFS)); in ddr3_read_leveling_single_cs_rl_mode()
719 add = (add >> (phase_min * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_read_leveling_single_cs_rl_mode()
1066 REG_TRAINING_DEBUG_3_OFFS); in ddr3_read_leveling_single_cs_window_mode()
1192 add = (add >> phase_min * REG_TRAINING_DEBUG_3_OFFS); in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_axp.h248 #define REG_TRAINING_DEBUG_3_OFFS 3 macro