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Searched refs:REG_FIELD_GET (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_color.c412 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); in i9xx_lut_8_pack()
413 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); in i9xx_lut_8_pack()
414 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); in i9xx_lut_8_pack()
435 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | in i965_lut_10p6_pack()
436 REG_FIELD_GET(PALETTE_RED_MASK, ldw); in i965_lut_10p6_pack()
437 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | in i965_lut_10p6_pack()
438 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); in i965_lut_10p6_pack()
439 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | in i965_lut_10p6_pack()
440 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); in i965_lut_10p6_pack()
458 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); in ilk_lut_10_pack()
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H A Dintel_lvds.c161 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
162 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
163 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
166 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
170 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
171 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
H A Dintel_dp.c6954 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
6955 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
6956 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
6957 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
6964 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
6966 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
H A Dintel_ddi.c4263 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); in bdw_transcoder_master_readout()
4270 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); in bdw_transcoder_master_readout()
4415 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); in intel_ddi_get_config()
H A Dintel_dpll_mgr.c3504 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state); in intel_get_hti_plls()
H A Dintel_display.c11271 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); in hsw_get_pipe_config()
11274 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); in hsw_get_pipe_config()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/
H A Di915_reg.h179 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) macro