Searched refs:PPLL_DIV_SEL_MASK (Results 1 – 4 of 4) sorted by relevance
222 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()223 ~PPLL_DIV_SEL_MASK); in radeon_write_pll_regs()242 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()243 ~PPLL_DIV_SEL_MASK); in radeon_write_pll_regs()
1368 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()1369 ~PPLL_DIV_SEL_MASK); in radeon_write_pll_regs()1386 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()1387 ~PPLL_DIV_SEL_MASK); in radeon_write_pll_regs()
985 #define PPLL_DIV_SEL_MASK 0x00000300 macro
989 #define PPLL_DIV_SEL_MASK 0x00000300 macro