Searched refs:PORT_LOGIC_LINK_WIDTH_MASK (Results 1 – 5 of 5) sorted by relevance
65 #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) macro66 #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
640 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; in dw_pcie_setup()
504 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; in rockchip_pcie_resize_bar()
1001 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; in rk_pcie_ep_setup()
67 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) macro277 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; in pcie_link_set_lanes()