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Searched refs:PORT_LOGIC_LINK_WIDTH_4_LANES (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c70 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) macro
286 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; in pcie_link_set_lanes()
/OK3568_Linux_fs/kernel/drivers/pci/controller/dwc/
H A Dpcie-designware.h69 #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) macro
H A Dpcie-designware.c649 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; in dw_pcie_setup()
H A Dpcie-dw-ep-rockchip.c513 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; in rockchip_pcie_resize_bar()
H A Dpcie-dw-rockchip.c1010 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; in rk_pcie_ep_setup()