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Searched refs:MXC_CCM_CCSR_PLL3_SW_CLK_SEL (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c676 writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL, in config_pll_clk()
682 writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL, in config_pll_clk()
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c1416 reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL; in select_ldb_di_clock_source()
1443 reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL; in select_ldb_di_clock_source()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h105 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 macro
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx6/
H A Dcrm_regs.h236 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) macro