Searched refs:EDPRSR (Results 1 – 3 of 3) sorted by relevance
70 #define EDPRSR 0x314 macro114 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_edpcsr()127 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_edpcsr()188 pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_pmpcsr()200 pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_pmpcsr()284 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_panic_notify_edpcsr()299 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_panic_notify_edpcsr()362 pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU; in rockchip_panic_notify_pmpcsr()372 pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU; in rockchip_panic_notify_pmpcsr()
34 #define EDPRSR 0x314 macro161 if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR, in debug_force_cpu_powered_up()183 drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR); in debug_force_cpu_powered_up()
108 This means that even checking EDPRSR has the potential to cause a bus hang184 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)189 coresight-cpu-debug 852000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)